XIANG Boqiang,LING Weiwei,LI Li,et al.FPGA-based Hardware Accelerator for RNN[J].Journal of Chengdu University of Information Technology,2022,37(04):374-378.[doi:10.16836/j.cnki.jcuit.2022.04.002]
基于FPGA的RNN硬件加速架构
- Title:
- FPGA-based Hardware Accelerator for RNN
- 文章编号:
- 2096-1618(2022)04-0374-05
- 关键词:
- 微电子学与固体电子学; 硬件加速器; 可编程逻辑器件; 循环神经网络; 指令集架构
- 分类号:
- TP183
- 文献标志码:
- A
- 摘要:
- 针对边缘计算场景下，循环神经网络消耗计算资源过多，且计算流程相对复杂所导致的计算效率较低的问题，提出一种RNN模型的硬件加速方法，并在FPGA平台对该方法进行验证。为在计算资源可复用的前提下尽可能提高计算速度，该加速器利用一种SIMD指令集，通过软件编程的形式来配置运算流程，适配不同层数和维度的RNN及其相关模型。还根据RNN模型数据流的特点，对加速器设计进行优化，并设置合理的片内缓存方式和并行逻辑以充分利用存储器带宽，降低资源开销。实验结果表明，加速器在100 MHz的工作频率下运算性能达到6.7 GOPS，需要的功耗为2.15 W。基于指令集和软硬件协同的方式对两种网络模型进行实现，速度是微控制器的230倍。
- Abstract:
- Aiming at the problem of low computing efficiency caused by the excessive consumption of computing resources and the complex computing process of Recurrent Neural Network in edge computing scenarios,the authors proposed a hardware acceleration method of RNN models and verified it on FPGA platform.To improve the processing speed under the premise that computing resources can be reused,the accelerator uses an SIMD instruction set,which can configure the operation flow in the form of software programming,and can adapt to different layers and dimensions of RNN and its related models. Moreover,according to the properties of RNN model’s data flow,the authors optimized the accelerator architecture with providing on-chip caches and parallel logic circuits to make full use of memory bandwidth and simultaneously reduce overhead.Experiments show that the performance of the accelerator reaches 6.7 GOPS at 100 MHz and the power consumption is 2.15 W.The two network models are implemented based on instruction set with the cooperation of software and hardware,and the speed is 230 times faster than that of the microcontroller.
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备注/Memo
收稿日期:2021-11-03
基金项目:国家自然科学基金资助项目(61201094)