WANG Sanxin.Design and Testing of an LED Driver Chip[J].Journal of Chengdu University of Information Technology,2024,39(06):695-701.[doi:10.16836/j.cnki.jcuit.2024.06.008]
一款LED驱动芯片的设计与测试
- Title:
- Design and Testing of an LED Driver Chip
- 文章编号:
- 2096-1618(2024)06-0695-07
- Keywords:
- row fading control; LED driver chip; FPGA; chip test
- 分类号:
- TN492
- 文献标志码:
- A
- 摘要:
- 在LED显示屏高刷新率、高扫描要求下,之前不被重视的LED反向漏电、寄生电容、寄生电感等因素导致的问题逐渐呈现出来。传统的控制方法容易出现拖影现象,且传统消隐芯片在LED老化后也可能出现毛毛虫现象。基于此设计一款专为LED动态扫描显示屏的8路行消隐控制芯片,消除拖影现象,集成消隐功能的行管,通过加入下拉电路进行切换时,对行寄生电容上的电荷进行提前泄放。主要集中解决以下2个核心问题:产生的消隐电压符合LED温漂系数且足够稳定准确,以及搭建测试平台测试消隐电压确保芯片达到设计要求。消隐电路的设定值可通过改变寄存器的值达到可选的消隐电压值,并在2 μs内实现端口电压下拉消隐。采用自顶向下的设计方法,结合硬件描述语言Verilog HDL,利用EDA开发工具及FPGA验证。最后通过XILINX FPGA芯片和示波器搭建一个测试系统对整个系统进行极限参数测试、功能测试和电路的电特性测试。结果表明在电源电压为5 V,工作频率为200 MHz的情况下,各项功能和性能达到设计指标要求。
- Abstract:
- Under the high refresh rate and high scanning requirement of LED display, the problems caused by LED reverse leakage, parasitic capacitance, parasitic inductance, and other factors that were not emphasized before are gradually presented. However, the traditional control method is prone to the phenomenon of dragging shadow, and the traditional fading chip may also appear a caterpillar phenomenon after LED aging. Based on this, we designed an 8-channel line blanking control chip specifically for LED dynamic scanning display, eliminating the phenomenon of shadow dragging, integrating the blanking function of the line tube, and releasing the charge on the line parasitic capacitor in advance by adding a pull-down circuit when switching. Mainly focus on solving the following two core issues:the resulting fade voltage in line with the LED temperature drift coefficient and sufficiently stable and accurate, as well as building a test platform to test the fade voltage to ensure that the chip meets the design requirements. The set value of the blanking circuit can be changed by changing the value of the register to achieve the optional blanking voltage value and realize the port voltage pull-down blanking within 2 μs.The top-down design method is used, combined with the hardware description language Verilog HDL, and verified by EDA development tools and FPGA. Finally, a test system is built by XILINX FPGA chip and oscilloscope to test the limit parameters of the whole system, functional test, and electrical characteristics of the circuit; the results show that the functions and performance meet the requirements of the design indexes at a power supply voltage of 5 V and an operating frequency of 200 MHz.
参考文献/References:
[1] 袁冶.高速消隐LED显示屏行控制电路的设计与实现[D].西安:西安电子科技大学,2020.
[2] 李梦杰,邓良,陈章进,等.基于控制串行传输的LED屏列驱动芯片设计[J].微电子学与计算机,2020,37(5):6-12.
[3] 杨保兴.一款可音频调制的LED显示驱动芯片的设计[D].西安:西安电子科技大学,2020.
[4] 杨燕妮.恒流LED驱动IC的静电浪涌防护设计[D].无锡:江南大学,2022.
[5] 殷录桥,张雪松,任开琳,等.考虑小尺寸效应的Micro-LED驱动结构设计[J].光学学报,2023,43(2):210-225.
[6] 周律,郑华,张声浩,等.Micro-LED显示及其驱动技术的研究进展[J].液晶与显示,2022,37(11):1395-1410.
[7] 王震宇,王雪原,唐茂洁,等.一种LED显示驱动芯片倍频OS-PWM算法[J].电子与封装,2022,22(1):67-71.
[8] 杨东.LED驱动电源的设计[J].黄河科技学院学报,2021,23(8):1-4.
[9] 周杨,冯奕,唐茂洁,等.一种LED显示屏补偿电路及其方法:中国专利,CN202010026192.9[P].2021-07-27.
[10] 汪苏,王兵,王美娟,等.基于FPGA的LED驱动芯片高速测试的设计与实现[J].电子技术与软件工程,2021,(20):65-68.
[11] 刘文斌,汪金辉,袁颖,等.一款SRAM芯片的设计与测试[J].微电子学,2014,44(4):495-498+502.
[12] 王展意.基于FPGA的存储芯片测试系统设计[J].中国集成电路,2021,30(5):64-73.
[13] 易美佳,李逍遥,金叶,等.基于LT3964的LED驱动电路的仿真与实验研究[J].照明工程学报,2022,33(1):76-80.
[14] 万垚,周咏.基于ZYNQ的视频处理平台框架设计[J].成都信息工程大学学报,2021,36(1):62-67.
[15] 王逸飞.基于FPGA的SoC全自动化测试平台的设计与实现[D].南京:东南大学,2021.
备注/Memo
收稿日期:2023-07-07