XIE Rong-fang,LI Zi-fu,YE Song.Design of Mode Configurable NAND Flash BCH Decoder[J].Journal of Chengdu University of Information Technology,2018,(04):353-358.[doi:10.16836/j.cnki.jcuit.2018.04.001]
纠错模式可配置的NAND Flash BCH译码器设计
- Title:
- Design of Mode Configurable NAND Flash BCH Decoder
- 文章编号:
- 2096-1618(2018)04-0353-06
- 关键词:
- 微电子学与固体电子学; 集成电路; NAND Flash; 模式可配置; BCH译码器; 低功耗
- Keywords:
- microelectronics and solid state electronics; integrated circuit; NAND Flash; mode configurable; BCH decoder; low power
- 分类号:
- TN432
- 文献标志码:
- A
- 摘要:
- 针对NAND Flash 的可靠性和使用寿命,完成一种模式可配置的BCH码的译码电路结构设计。结构实现了(8640,8192,32)、(8416,8192,16)、(8304,8192,8)3种模式的BCH码译码电路,可根据存储器误码率配置译码模式,通过合理配置译码电路内部资源,减小功耗。译码器采用求余式的校正子求解法、SiBM迭代算法、有限域固定因子乘法器的并行钱氏搜索算法。与单纠错模式的BCH码(8640,8192,32)相比,在只增加极少硬件资源开销的情况下,使低误码率时译码器的功耗大幅减少。优化后的纠错能力t=8的BCH译码器,校正子结构、钱氏搜索结构分别节约了49.1%、64.9%的功耗,纠错能力t=16的BCH译码器,校正子结构、钱氏搜索结构分别节约了34.0%、42.4%的功耗。译码器基于Xilinx公司Zynq系列芯片,在Xilinx Vivado上完成了电路仿真与验证。
- Abstract:
- Aiming at the reliability and lifetime of the NAND Flash memory, a mode configurable BCH decoding circuit structure is implemented. The structure achieves three modes of(8640,8192,32),(8416,8192,16),(8304,8192,8)BCH decoding circuit which can be configured according to the memory bit error rate(BER), the power consumption is reduced by rationally configuring the internal resources of the decoding circuits. The decoder solves syndromes by remainder, and adopts simplified inversionless Berlekamp Massey(SiBM)iterative algorithm and Constant Finite Field Multiplier(CFFM)in the parallel Chien search algorithm. Compared with the single mode of BCH code(8640, 8192, 32), the proposed design which significantly reduces the power consumption in the case of low BER decoder sacrificing only a few hardware resources consumption. For the optimized BCH decoder of error correcting capability t=8, the Syndrome structure, Chien search structures are of 49.1%,64.9% power saving. And for the BCH decoder of t=16, the power saving are 34.0% and 42.4% respectively. The decoder is based on the Xilinx Zynq series chip and the circuit simulation and verification is done by Xilinx Vivado.
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备注/Memo
收稿日期:2018-03-12基金项目:国家自然科学基金资助项目(61474137)