LIU Jujing,WANG Haishi,HU Shipeng.Design of a High Speed and Low Power Comparator[J].Journal of Chengdu University of Information Technology,2021,36(01):15-18.[doi:10.16836/j.cnki.jcuit.2021.01.003]
一种高速低功耗比较器设计
- Title:
- Design of a High Speed and Low Power Comparator
- 文章编号:
- 2096-1618(2021)01-0015-04
- Keywords:
- comparator Integrated circuit; analog to digital conversion circuit; comparator; preamplifier circuit; latch
- 分类号:
- TN432
- 文献标志码:
- A
- 摘要:
- 模数转换电路的性能优化不断推进比较器电路的发展,适用于高速低功耗的比较器是集成电路设计的主要发展方向。给出一种动态比较器,使用动态预放大电路结构实现低功耗高速度比较器特性,前置放大器能够增强响应速度,同时还可以有效减小失调电压对性能造成的影响。仿真结果显示当时钟频率35 M,1.5 V电源电压仿真环境下比较器平均功耗82 μW,精度小于1 mV,失调电压小于0.5 mV。
- Abstract:
- The performance optimization of analog digital converter promotes the development of comparator circuit, and the comparator which is suitable for high speed and low power consumption is the main development direction at present. The dynamic comparator presented in this paper is using a dynamic preamplifier circuit structure to realize the characteristics of low power consumption and high speed comparator. The preamplifier can enhance the speed of comparator and reduce the offset voltage conditions of comparator effectively in the same time. The simulation results show that the clock frequency is 35 M, when the power supply voltage is 1.5 V, average power consumption of the comparator is 82 μW, the precision of comparator is less than 1mV, and the offset voltage is less than 0.5 mV.
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备注/Memo
收稿日期:2020-06-12
基金项目:四川省2018-2020年高等教育人才培养质量和教学改革资助项目(JG2018-523)