HUANG Yangyang,CHEN Changming.Low Phase Noise PFD based on ECL Structure[J].Journal of Chengdu University of Information Technology,2022,37(04):401-405.[doi:10.16836/j.cnki.jcuit.2022.04.007]
基于发射极耦合逻辑结构的低相噪鉴频鉴相器设计
- Title:
- Low Phase Noise PFD based on ECL Structure
- 文章编号:
- 2096-1618(2022)04-0401-05
- Keywords:
- PLL; PFD; ECL; 1/f noise; phase noise
- 分类号:
- TN432
- 文献标志码:
- A
- 摘要:
- 在现代通信系统中，具有优异相位噪声的鉴频鉴相器(phase frequency detector，PFD)对锁相环(phase locked loop，PLL)来说至关重要。基于0.18 μm SiGe HBT工艺设计一款超低相噪PFD。为消除鉴相死区对PLL相位噪声的影响，加入复位延时单元。PFD的逻辑电路均采用发射级耦合逻辑(emitter coupled logic，ECL)结构，从而获得-156 dBc/Hz@10 kHz超低相噪特性。在5 V电源电压下，PFD的工作频率可以达到1 GHz，且在复位脉冲宽度为145 ps时鉴相范围拓宽到[-1.56π，1.56π]。
- Abstract:
- Phase frequency detectors(PFD)with excellent phase noise performance are critical for phase lock loops(PLL)in modern communication systems. Based on a 0.18 μm SiGe HBT process,an ultra-low phase noise PFD is designed and analyzed. In order to eliminate the influence of the phase-detection dead region on the PLL phase noise,a reset delay unit is added in this schematic. Owing to all the logic circuits in this PFD utilizing emitter coupled logic(ECL),an excellent ultra-low phase noise of -156 dBc/Hz@10 kHz is obtained. Under the condition of 5 V supply,the operating frequency of the designed PFD can reach 1 GHz,and the phase-detection range is extended to [-1.56π,1.56π] using a reset pulse width of 145 ps.
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备注/Memo
收稿日期:2021-12-20