ZHANG Jun,WANG Duorong,ZHANG Lingyu,et al.Implementation of Digital Channelized Receiver based on ZYNQ[J].Journal of Chengdu University of Information Technology,2023,38(05):521-525.[doi:10.16836/j.cnki.jcuit.2023.05.005]
基于ZYNQ的数字信道化接收机实现
- Title:
- Implementation of Digital Channelized Receiver based on ZYNQ
- 文章编号:
- 2096-1618(2023)05-0521-05
- Keywords:
- time-division multiplexing; polyphase DFT; digital channelized receiver; ZYNQ; CORDIC algorithm
- 分类号:
- TN851
- 文献标志码:
- A
- 摘要:
- 在现代电子战中，针对数字信道化接收机瞬时覆盖宽带大、灵敏度高、动态范围大和多信号并行处理的问题，提出一种基于时分复用的多相DFT的数字信道化结构接收机的方法。该接收机以异构芯片ZYNQ为平台，以高速ADC对中频模拟信号进行采样，利用CORDIC算法提取基于时分复用的数字信道化结构输出的幅度及相位，经过检波脉冲修正后，将组帧数据通过AXI DMA从PL端传输至PS端进行后续处理，在可编程阵列逻辑(FPGA)硬件平台上低耗实现基于时分复用的数字信道化结构的脉冲参数测量和AXI DMA数据传输等功能。经过反复测试表明，基于时分复用的多相DFT的数字信道化接收机，完成了对信号的高速采样，实现接收机的数字信道化处理，减少了78%的硬件乘法器资源，符合设计要求。
- Abstract:
- In modern electronic warfare, to address the issues of wide instantaneous bandwidth, high sensitivity, large dynamic range, and multi-signal parallel processing of digital channelized receivers, a method based on time-division multiplexing and polyphase DFT is proposed in this paper. This receiver is implemented on the heterogeneous chip ZYNQ platform, which samples the IF(Intermediate Frequency)analog signal with high-speed ADC. And the CORDIC algorithm is used to extract the amplitude and phase of the digital channelized structure output based on time-division multiplexing. After the demodulation pulse correction, the frame data is transmitted from the PL side to the PS side through AXI DMA for subsequent processing. The pulse parameter measurement of the digital channelized structure based on time-division multiplexing and AXI DMA data transmission functions are implemented on the programmable logic(FPGA)hardware platform with low power consumption. After repeated testing, it is shown that the digital channelized receiver based on time-division multiplexing and multi-phase DFT completes the high-speed sampling of the signal, achieves the digital channelization processing of the receiver, and reduces 78% of the hardware multiplier resources, which meets the design requirements.
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备注/Memo
收稿日期:2022-10-11
基金项目:四川省科技厅重点研发资助项目(2022YFS0385)